1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a static random access memory (SRAM with a reduced standby current.
2. Description of the Background Art
FIG. 16 is a circuit diagram showing the configuration of a memory cell array 800 of a conventional SRAM.
Referring to FIG. 16, conventional memory cell array 800 includes a plurality of word lines WL1, WL2, . . . and a plurality of bit lines BL1, /BL1, BL2, /BL2, . . .
Bit lines BL1 and /BL1 form a bit line pair BLP1. Bit lines BL2 and /BL2 form a bit line pair BLP2.
Memory cell array 800 further includes: a load circuit 802 connected to bit line pair BLP1 and a plurality of memory cells 804 provided at intersecting points of bit line pair BLP1 and word lines WL1, WL2, . . . Similarly, memory cell array 800 includes load circuit 802 and plurality of memory cells 804 provided at intersecting points of bit line pair BLP2 and word lines.
Load circuit 802 includes a P-channel MOS transistor 806 connected between bit line BL1 and a power supply node and having a gate coupled to the ground potential, and a P-channel MOS transistor 808 connected between complementary bit line /BL1 and the power supply node and having a gate coupled to the ground potential.
Load circuit 802 is provided to read data from a memory cell at high speed. Specifically, the bit lines are precharged to the power supply potential by P-channel MOS transistors 806 and 808 of high resistance which are always conductive. When a word line is activated, by a driver transistor of the memory cells, one of the bit lines in the pair is pulled down. A sense amplifier connected to the bit line pair detects a slight potential difference which occurs between the bit lines of the pair and reads data at high speed.
Consequently, even when the driving force of the driver transistor of the memory cells is not so strong, data held in a memory cell can be read at high speed via the bit lines.
Memory cell 804 includes: an N-channel MOS transistor 810 connected between the bit line and a node N55 and having a gate connected to the word line; a P-channel MOS transistor 816 connected between the power supply node and a node N56 and having a gate connected to node N55; an N-channel MOS transistor 818 connected between a node N56 and the ground node and having a gate connected to node N55; an N-channel MOS transistor 820 connected between node N56 and the complementary bit line and having a gate connected to the word line; a P-channel MOS transistor 812 connected between the power supply node and node N55 and having gate connected to node N56; and an N-channel MOS transistor 814 connected between node N55 and the ground node and having a gate connected to node N56.
Memory cell array 800 includes a first ground line LG1 disposed adjacent to and parallel to bit line BL1 and a second ground line LG2 disposed adjacent to and parallel to bit line BL2.
In a manufacturing process, due to dusts or the like, there is a case that a short circuit occurs between bit line BL1 and ground line LG1 as shown by an arrow in FIG. 16. When such a failure occurs, data cannot be transmitted/received to/from the memory cell column connected to bit line BL1.
FIG. 17 is a diagram for explaining the failure occurred in the memory array.
Referring to FIG. 17, a case where a short circuit is caused by a foreign matter 836 between a ground line LG1 and a bit line BL1 is shown. Bit line BL1 in FIG. 17 corresponds to bit line BL1 in FIG. 16, and ground line BL1 in FIG. 17 corresponds to ground line LG1 adjacent to bit line BL1 in FIG. 16. In such a case, the memory cell column connected to bit line BL1 becomes defective and is repaired by a redundancy circuit provided in the memory cell.
However, when the defective portion is left, an unnecessary current flows from the power supply node to ground line LG1 via load circuit 802 and the bit line. In such a case, a problem arises such that a current in a standby mode in which writing and reading operations can be normally performed, that is, a standby current increases.
FIG. 18 is a circuit diagram showing a path of the current passed due to a failure which occurs in another position.
Referring to FIG. 18, a case where a short circuit occurs between the power supply node and the ground node in a memory cell is shown. Even in the case where such a short circuit occurs, after the failure is repaired by the redundancy circuit, the reading and writing operations can be normally performed. However, a problem such that a current in the standby mode increases occurs likewise.
An SRAM is often used in a portable telephone and a portable information device which are actively commercialized in recent years since control on the SRAM is easier than that on a dynamic random access memory or the like. Since each of the portable devices is driven on a battery, the current consumption in the standby mode is requested to be as little as possible. Consequently, when a current increases in the standby mode due to some factor, even if the other operations are normal, the device is a defective. It causes deterioration in yield.
Conventionally, repairing operation using a redundancy circuit is conducted to repair a failure which increases the standby current.
FIG. 19 is a circuit diagram showing the configuration of a memory cell array of a conventional SRAM disclosed in Japanese Patent Laying-Open No. 7-45093.
Referring to FIG. 19, the memory cell is provided with a power supply line 901 through which the power supply potential is supplied, a ground line 902 through which a ground potential for memory cells is supplied, and a power supply line 910 through which a power supply potential for memory cells is supplied.
To the memory cell array, a precharge signal for controlling the gates of bit line load transistors 923, 924, 933, and 934 is supplied via a signal line 903. Via a signal line 904, an equalize signal for controlling the gate of an N-channel transistor 912 which short-circuits a pair of normal bit lines 906a and 906b connected to normal memory cells and short-circuits a pair of spare bit lines 907a and 907b connected to spare memory cells is supplied.
When a word line 905 is made active, memory cells 911 are selected.
In the case where an error bit occurs in the normal memory cell array, the normal memory cell column in which the error bit exists is not selected but a first spare memory cell column is selected with respect to the same address, thereby enabling an operation error of the semiconductor memory device to be prevented.
A bit line load circuit 917 of the pair of normal bit lines 906a and 906b includes: a first load circuit having N-channel MOS transistors 921 and 922 whose gates are connected to the ground potential; and a second load circuit having N-channel MOS transistors 923 and 924 having gates to which a precharge signal is supplied via signal line 903.
A control signal generating circuit 940 is provided to control a bit line load circuit 918 of a pair of spare bit lines 907a and 907b. 
Control signal generating circuit 940 receives a precharge signal via signal line 903 and receives a spare bit line pair control signal indicative of whether the spare memory cell column is used or not via a signal line 906. The spare bit line pair control signal is set to the L level when the spare memory cell column is used, and is set to the H level when the spare memory cell column is not used.
In the case where a short circuit occurs due to a particle existing between the spare memory cell column and a ground potential line, the first spare memory cell column can not be used as a spare memory cell column. In this case, a spare bit line pair control signal is fixed at the H level, so that a signal line 942 becomes the L level. In bit line load circuit 918 of the pair of spare bit lines 907a and 907b, N-channel MOS transistors 931 and 932 are made non-conductive.
Although the conventional SRAM shown in FIG. 19 is effective in preventing an increase in the standby current caused by a failure occurred in a spare bit line, it has a problem such that an increase in the standby current due to a failure occurred in another portion in the memory array cannot be prevented.
Moreover, a control signal for interrupting a current path has to be supplied to an unused spare bit line by a setting from the outside. In the case of a memory cell column which does not operate normally and an unused memory cell column, it is possible to supply a control signal from the outside to interrupt a current path. However, in the case such that a short circuit occurs with high resistance between the bit line and the ground line, since the reading and writing operation is performed normally, such a control signal cannot be supplied. It consequently causes a problem such that a failure occurring out of the standby current specification cannot be repaired.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.